A semiconductor memory, for example a dynamic random access semiconductor memory, a so-called DRAM (dynamic random access memory) comprises, in particular, a semiconducting substrate, an array of memory cells, an address bus for application of a memory address, an address decoder for selection of one of the memory cells on the basis of the memory address and a data bus for reading or writing access to the information stored in the selected memory cell.
The array of memory cells is subdivided into rows and columns and comprises a plurality of word lines and a plurality of bit lines for reading and writing access to the memory cells. A respective one of the memory cells is connected to one of the word lines and to one of the bit lines. A respective one of the word lines is connected to the memory cells of one of the rows of the array. A respective one of the bit lines is connected to the memory cells of one of the columns of the array.
Each of the memory cells of the array contains a selection transistor having a control terminal and a controlled path and a storage capacitor having a first electrode and a second electrode. The second electrodes of the storage capacitors of the memory cells of the array are electrically conductively connected to one another.
The information stored in a selected memory cell is defined by the sign of a cell voltage. The cell voltage is a difference in the voltages between the first and second electrodes of the storage capacitor. The cell voltage has to be periodically refreshed, while retaining the sign to an initial value defined beforehand in order to counteract an exponential decrease over time that is brought about by leakage currents. The initial value and the decrease over time of the cell voltage determines a retention time within which the memory cell has to be refreshed again.
The semiconductor memory usually comprises a semiconducting substrate and the storage capacitor of one of the memory cells is formed as a trench capacitor in the semiconducting substrate. For this purpose, a trench is etched into the semiconducting substrate, the second electrode is formed as a highly doped electrode buried in the substrate and is arranged around the trench, a node dielectric is applied on that surface of the substrate which is located in the interior of the trench, and the first electrode is deposited as a highly doped trench electrode in the trench. Furthermore, the second electrodes of the memory cells are connected to one another by forming a highly doped region buried in the substrate. The highly doped region buried in the substrate is also referred to as a buried plate.
During the operation of the semiconductor memory, a constant predetermined voltage, the so-called plate voltage VPL, is applied to the plate buried in the substrate. Supplying the buried plate with voltage necessitates a contact connection.
The buried plate is usually contact-connected via a highly doped contact well adjacent to the surface of the substrate. For its part, the contact well is connected to the plate voltage VPL via a highly doped lead, for instance made of polysilicon.
In general, the contact well extends between a part of the surface of the substrate that surrounds the array of memory cells and the buried plate. In this way, the contact well and the buried plate isolate an array well, in which the storage capacitors of the memory cells of the array are formed, from a peripheral well, in which the support circuits of the memory cell array are formed.
It is also possible for the array well to be surrounded by an isolation well and for the isolation well to be surrounded by the peripheral well. The isolation well then comprises both the buried plate and the contact well.
The buried plate and the contact well have a comparatively low specific conductivity. Furthermore, the trenches of the storage capacitors of the memory cells extend deep into the buried plate. As a result, the cross section of conductive material is reduced for a current flowing along the buried plate. Furthermore, the buried plate is contact-connected along the edge of the array of memory cells. As a result, the distance between the contact well and the second electrode of one of the memory cells is very large on average. Since the second electrode of one of the memory cells is on average connected to the plate voltage VPL with very high impedance, the time constant for changes in the potential at the location of the second electrode is large and the value of the potential is poorly controllable. In particular, the initial value of the cell voltage that is produced during the refresh of one of the memory cells may be too small. The resultant shortening of the retention time may lead to a loss of the stored information.